View FM93C46ALEM8_2435847.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) july 2000 ?2000 fairchild semiconductor international fm93c46a 1k-bit serial cmos eeprom (microwire? synchronous bus) general description fm93c46a is a 1024-bit cmos non-volatile eeprom organized as 64 x 16-bit array. this device features microwire interface which is a 4-wire serial bus with chipselect (cs), clock (sk), data input (di) and data output (do) signals. this interface is compat- ible to many standard microcontrollers and microprocessors. this device offers a pin (org), using which, the user can select the format of the data (16-bit or 8-bit). if org is tied to gnd, then 8- bit format is selected, while if org is tied to v cc , then 16-bit format is selected. there are 7 instructions implemented on the fm93c46a for various read, write, erase, and write enable/disable opera- tions. this device is fabricated using fairchild semiconductor floating-gate cmos process for high reliability, high endurance and low power consumption. ?z?and ??versions of fm93c46a offer very low standby current making them suitable for low power applications. this device is offered in both so and tssop packages for small space consid- erations. functional diagram features wide v cc 2.7v - 5.5v user selectable organization x16 (org = 1) x8 (org = 0) typical active current of 200 a 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) no erase instruction required before write instruction self timed write cycle device status during programming cycles 40 year data retention endurance: 1,000,000 data changes packages available: 8-pin so, 8-pin dip, 8-pin tssop instruction decoder control logic and clock generators high voltage generator and program timer instruction register address register eeprom array read/write amps data in/out register 16/8 bits decoder 16 16 data out buffer cs sk di org do v ss v cc
2 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) connection diagram dual-in-line package (n) 8Cpin so (m8) and 8Cpin tssop (mt8) top view package number n08e, m08a and mtc08 pin names cs chip select sk serial data clock di serial data input do serial data output gnd ground org organization nc no connect v cc power supply note: pins designated as "nc" are typically unbonded pins. however some of them are bonded for special testing purposes. hence if a s ignal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the v cc applied to the device. this will ensure proper operation. ordering information fm 93 c xx a t lz e xxx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current blank normal pinout t rotated pinout a x8 or x16 configuration density 46 1024 bits c cmos cs data protect and sequential read interface 93 microwire fairchild memory prefix v cc org gnd cs sk di do 1 2 3 4 8 7 6 5 nc org do di nc v cc cs sk 1 2 3 4 8 7 6 5 gnd normal pinout rotated pinout
3 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature fm93c46a 0 c to +70 c fm93c46ae -40 c to +85 c fm93c46av -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics v cc = 4.5v to 5.5v unless otherwise specified symbol parameter conditions min max units i cca operating current cs = v ih , sk=1.0 mhz 1 ma i ccs standby current cs = v il 50 a i il input leakage v in = 0v to v cc -1 a i ol output leakage (note 2) i ilo input leakage org pin org tied to v cc -1 1 a org tied to v ss (note 3) -2.5 2.5 v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 a 2.4 v ol2 output low voltage i ol = 10 a 0.2 v v oh2 output high voltage i oh = -10 av cc - 0.2 f sk sk clock frequency (note 4) 1 mhz t skh sk high time 0 c to +70 c 250 ns -40 c to +125 c 300 t skl sk low time 250 ns t cs minimum cs low time (note 5) 250 ns t css cs setup time 50 ns t dh do hold time 70 ns t dis di setup time 100 ns t csh cs hold time 0 ns t dih di hold time 20 ns t pd output delay 500 ns t sv cs to status valid 500 ns t df cs to do in hi-z cs = v il 100 ns t wp write cycle time 10 ms
4 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature fm93c46al/lz 0 c to +70 c fm93c46ale/lze -40 c to +85 c fm93c46alv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 5.5v dc and ac electrical characteristics v cc = 2.7v to 4.5v unless otherwise specified. refer to page 3 for v cc = 4.5v to 5.5v symbol parameter conditions min max units i cca operating current cs = v ih , sk=250 khz 1 ma i ccs standby current cs = v il l 10 a lz (2.7v to 4.5v) 1 a i il input leakage v in = 0v to v cc 1 a i ol output leakage (note 2) i ilo input leakage org pin org tied to v cc -1 1 a org tied to v ss (note 3) -2.5 2.5 v il input low voltage -0.1 0.15v cc v v ih input high voltage 0.8v cc v cc +1 v ol output low voltage i ol = 10 a 0.1v cc v v oh output high voltage i oh = -10 a 0.9v cc f sk sk clock frequency (note 4) 0 250 khz t skh sk high time 1 s t skl sk low time 1 s t cs minimum cs low time (note 5) 1 s t css cs setup time 0.2 s t dh do hold time 70 ns t dis di setup time 0.4 s t csh cs hold time 0 ns t dih di hold time 0.4 s t pd output delay 2 s t sv cs to status valid 1 s t df cs to do in hi-z cs = v il 0.4 s t wp write cycle time 15 ms capacitance t a = 25 c, f = 1 mhz or 250 khz (note 6) symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20na range. note 3 : org pin may draw >1 a when in x8 mode due to the internal pull-up transistor. note 4 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 5 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagram on the following page.) note 6 : this parameter is periodically sampled and not 100% tested. ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v 0.3v/1.8v 1.0v 0.8v/1.5v 10 a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v 2.1ma/-0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf)
5 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) pin description chip select (cs) this is an active high input pin to fm93c46a eeprom (the device) and is generated by a master that is controlling the device. a high level on this pin selects the device and a low level deselects the device. all serial communications with the device is enabled only when this pin is held high. however this pin cannot be permanently tied high, as a rising edge on this signal is required to reset the internal state-machine to accept a new cycle and a falling edge to initiate an internal programming after a write cycle. all activity on the sk, di and do pins are ignored while cs is held low. serial clock (sk) this is an input pin to the device and is generated by the master that is controlling the device. this is a clock signal that synchronizes the communication between a master and the device. all input informa- tion (di) to the device is latched on the rising edge of this clock input, while output data (do) from the device is driven from the rising edge of this clock input. this pin is gated by cs signal. serial input (di) this is an input pin to the device and is generated by the master that is controlling the device. the master transfers input informa- tion (start bit, opcode bits, array addresses and data) serially via this pin into the device. this input information is latched on the rising edge of the sck. this pin is gated by cs signal. serial output (do) this is an output pin from the device and is used to transfer output data via this pin to the controlling master. output data is serially shifted out on this pin from the rising edge of the sck. this pin is active only when the device is selected. organization (org) this is an input pin to the device and is used to select the format of data (16-bit or 8-bit). if this pin is tied high, 16-bit format is selected, while if it is tied low, 8-bit format is selected. depending on the format selected, fm93c46a requires 6-bit address field (for 16-bit data format) or 7-bit address field (for 8-bit data format). refer table 1 and table 2 for more details. this pin is internally pulled-up to v cc . hence leaving this pin unconnected would default to 16-bit data format. microwire interface a typical communication on the microwire bus is made through the cs, sk, di and do signals. to facilitate various operations on the memory array, a set of 7 instructions are implemented on fm93c46a. the format of each instruction is listed under table 1 (for 16-bit format) and table 2 (for 8-bit format). instruction each of the above 7 instructions is explained under individual instruction descriptions. start bit this is a 1-bit field and is the first bit that is clocked into the device when a microwire cycle starts. this bit has to be 1 for a valid cycle to begin. any number of preceding 0 can be clocked into the device before clocking a 1 . opcode this is a 2-bit field and should immediately follow the start bit. these two bits (along with 2 msb of address field) select a particular instruction to be executed. address field depending on the selected organization, this is a 6-bit or 7-bit field and should immediately follow the opcode bits. in fm93c46a, all 6 bits (or 7 bits) are used for address decoding during read, write and erase instructions. during all other instructions, the msb 2 bits are used to decode instruction (along with opcode bits). data field depending on the selected organization, this is a 16-bit or 8-bit field and should immediately follow the address bits. only the write and wrall instructions require this field. msb bit (d15 or d7) is clocked first and lsb bit (d0) is clocked last (both during writes as well as reads). table 1. instruction set (16-bit organization) instruction start bit opcode field address field data field read 1 10 a5 a4 a3 a2 a1 a0 wen 1 00 1 1xxxx write 1 01 a5 a4 a3 a2 a1 a0 d15-d0 wrall 1 00 0 1 xxxx d15-d0 wds 1 00 0 0xxxx erase 1 11 a5 a4 a3 a2 a1 a0 eral 1 00 1 0 xxxx
6 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) functional description a typical microwire cycle starts by first selecting the device (bringing the cs signal high). once the device is selected, a valid start bit ( 1 ) should be issued to properly recognize the cycle. following this, the 2-bit opcode of appropriate instruction should be issued. after the opcode bits, the 6-bit (or 7-bit) address information should be issued. for certain instructions, some of the bits of this field are don t care values (can be 0 or 1 ), but they should still be issued. following the address information, depend- ing on the instruction (write and wrall), 16-bit data (or 8-bit) is issued. otherwise, depending on the instruction (read), the device starts to drive the output data on the do line. other instructions perform certain control functions and do not deal with data bits. the microwire cycle ends when the cs signal is brought low. however during certain instructions, falling edge of the cs signal initiates an internal cycle (programming), and the device remains busy till the completion of the internal cycle. each of the 7 instructions is explained in detail in the following sections. 1) read (read) read instruction allows data to be read from a selected location in the memory array. input information (start bit, opcode and address) for this instruction should be issued as listed under table 1 or table 2. upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer from the selected memory location into a 16-bit serial-out shift register. this 16-bit data (or 8-bit data) is then shifted out on the do pin. msb of the data (d15 or d8) is shifted out first and lsb (do) is shifted out last. a dummy-bit (logical 0) precedes this data output string. output data changes are initiated on the rising edge of the sk clock. after reading the 16-bit (or 8-bit) data, the cs signal can be brought low to end the read cycle. refer read cycle diagram . 2) write enable (wen) when v cc is applied to the part, it powers up in the write disable (wds) state. therefore, all programming operations must be preceded by a write enable (wen) instruction. once a write enable instruction is executed, programming remains enabled until a write disable (wds) instruction is executed or v cc is completely removed from the part. input information (start bit, opcode and address) for this wen instruction should be issued as listed under table 1 or table 2. the device becomes write- enabled at the end of this cycle when the cs signal is brought low. execution of a read instruction is independent of wen instruc- tion. refer write enable cycle diagram. 3) write (write) write instruction allows write operation to a specified location in the memory with a specified data. this instruction is valid only when device is write-enabled (refer wen instruction). input information (start bit, opcode, address and data) for this write instruction should be issued as listed under table 1 or table 2. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical charac- teristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. the status of the internal programming cycle can be polled at any time by bringing the cs signal high again, after t cs interval. when cs signal is high, the do pin indicates the ready/busy status of the chip. do = logical 0 indicates that the programming is still in progress. do = logical 1 indicates that the programming is finished and the device is ready for another instruction. it is not required to provide the sk clock during this status polling. while the device is busy, it is recommended that no new instruction be issued. refer write cycle diagram. it is also recommended to follow this instruction (after the device becomes ready) with a write disable (wds) instruction to safeguard data against corruption due to spurious noise, inadvert- ent writes etc. 4) write all (wrall) write all (wrall) instruction is similar to the write instruction except that wrall instruction will simultaneously program all memory locations with the data pattern specified in the instruction. this instruction is valid only when device is write-enabled (refer wen instruction). input information (start bit, opcode, address and data) for this wrall instruction should be issued as listed under table 1 or table 2. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical charac- teristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer write all cycle diagram. table 2. instruction set (8-bit organization) instruction start bit opcode field address field data field read 1 10 a6 a5 a4 a3 a2 a1 a0 wen 1 00 1 1xxxxx write 1 01 a6 a5 a4 a3 a2 a1 a0 d7-d0 wrall 1 00 0 1 xxxxx d7-d0 wds 1 00 0 0xxxxx erase 1 11 a6 a5 a4 a3 a2 a1 a0 eral 1 00 1 0 xxxxx
7 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) 5) write disable (wds) write disable (wds) instruction disables all programming opera- tions and should follow all programming operations. executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvert- ent writes etc. input information (start bit, opcode and address) for this wds instruction should be issued as listed under table 1 or table 2. the device becomes write-disabled at the end of this cycle when the cs signal is brought low. execution of a read instruction is independent of wds instruction. refer write disable cycle diagram. 6) erase (erase) the erase instruction will program all bits in the specified location to logical 1 state. input information (start bit, opcode and address) for this wds instruction should be issued as listed under table 1 or table 2. after inputting the last bit of data (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruc- tion be issued. refer erase cycle diagram. 7) erase all (eral) the erase all instruction will program all locations to logical 1 state. input information (start bit, opcode and address) for this wds instruction should be issued as listed under table 1 or table 2. after inputting the last bit of data (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer erase all cycle diagram. note: the fairchild cmos eeproms do not require an erase or erase all instruction prior to the write or write all instruction, respectively. the erase and erase all instructions are included to maintain compatibility with earlier technology eeproms. clearing of ready/busy status when programming is in progress, the data-out pin will display the programming status as either busy (low) or ready (high) when cs is brought high (do output will be tri-stated when cs is low). to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affecting the programming operation. once programming is completed (output in ready state), the output is cleared (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. refer clearing ready status diagram. related document application note: an758 - using fairchild s microwire ee- prom.
8 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) t css synchronous data timing cs sk di do (data read) do (status read) valid status t dis t dih t pd t dh t sv t skh t skl t csh t df t df t pd valid input valid input valid output valid output cs sk di do high - z dummy bit 1 1 0 a1 a0 0 d1 d0 t cs read cycle (read) address bits(6/7) start bit opcode bits(2) 93c46a (org=1; a n =a5; d n =d15 ): address bits pattern -> a5-a4-a3-a2-a1-a0; user defined 93c46a (org=0; a n =a6; d n =d7 ): address bits pattern -> a6-a5-a4-a3-a2-a1-a0; user defined a n a n-1 d n timing diagrams address bits(6/7) cs sk di do high - z write enable cycle (wen) start bit opcode bits(2) 1 0 0 a1 a0 t cs a n a n-1 93c46a (org=1; a n =a5 ): address bits pattern -> 1-1-x-x-x-x; (x -> don t care, can be 0 or 1) 93c46a (org=0; a n =a6 ): address bits pattern -> 1-1-x-x-x-x-x; (x -> don t care, can be 0 or 1)
9 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) timing diagrams (continued) address bits(6/7) cs sk di do high - z write disable cycle (wds) start bit opcode bits(2) 1 0 0 a1 a0 t cs 93c46a (org=1; a n =a5 ): address bits pattern -> 0-0-x-x-x-x; (x -> don t care, can be 0 or 1) 93c46a (org=0; a n =a6 ): address bits pattern -> 0-0-x-x-x-x-x; (x -> don t care, can be 0 or 1) a n a n-1 address bits(6/7) data bits(16/8) cs sk di do high - z t cs write cycle (write) start bit 93c46a (org=1; a n =a5; d n =d15 ): address bits pattern -> a5-a4-a3-a2-a1-a0; user defined data bits pattern -> d15-to-d0; user defined 93c46a (org=0; a n =a6; d n =d7 ): address bits pattern -> a6-a5-a4-a3-a2-a1-a0; user defined data bits pattern -> d7-to-d0; user defined opcode bits(2) 1 0 1 a n a n-1 a1 a0 d n d n-1 d1 d0 busy ready t wp address bits(6/7) data bits(16/8) cs sk di do high - z t cs write all cycle (wrall) start bit opcode bits(2) 1 0 0 a1 a0 d1 d0 busy ready t wp 93c46a (org=1; a n =a5; d n =d15 ): address bits pattern -> 0-1-x-x-x-x; (x -> don't care, can be 0 or 1) data bits pattern -> d15-to-d0; user defined 93c46a (org=0; a n =a6; d n =d7 ): address bits pattern -> 0-1-x-x-x-x-x; (x -> don't care, can be 0 or 1) data bits pattern -> d7-to-d0; user defined a n a n-1 d n d n-1
10 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) timing diagrams (continued) cs sk di do high - z high - z clearing ready status start bit note: this start bit can also be part of a next instruction. hence the cycle can be continued(instead of getting terminated, as shown) as if a new instruction is being issued. busy ready address bits(6/7) cs sk di do high - z t cs erase cycle (erase) start bit opcode bits(2) 1 1 1 a1 a0 busy ready t wp a n a n-1 93c46a (org=1; a n =a5): address bits pattern -> a5-a4-a3-a2-a1-a0; user defined 93c46a (org=0; a n =a6 ): address bits pattern -> a6-a5-a4-a3-a2-a1-a0; user defined address bits(6/7) cs sk di do high - z t cs erase all cycle (eral) start bit opcode bits(2) 1 0 0 a1 a0 busy ready t wp 93c46a (org=1; a n =a5 ): address bits pattern -> 1-0-x-x-x-x; (x -> don t care, can be 0 or 1) 93c46a (org=0; a n =a6 ): address bits pattern -> 1-0-x-x-x-x-x; (x -> don t care, can be 0 or 1) a n a n-1
11 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) molded package, small outline, 0.15 wide, 8-lead (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.004 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
12 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) 8-pin molded tssop, jedec (mt8) package number mtc08 physical dimensions inches (millimeters) unless otherwise noted 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0118 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
13 www.fairchildsemi.com fm93c46a rev. c.1 fm93c46a 1k-bit serial cmos eeprom (microwire tm synchronous bus) physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841

▲Up To Search▲

Price & Availability of FM93C46ALEM8

	To Download FM93C46ALEM8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .